Field of the Invention
Embodiments of the invention relate generally to multithreaded processing and, more specifically, to a set of instructions that enable application software to manage a parallel cache hierarchy in a parallel thread processor.
Description of the Related Art
Conventional cache policy techniques attempt to determine a pattern of load and store operations in an effort to anticipate which data should be cached and/or evicted. However, in a highly multithreaded parallel processor, it can be extremely difficult to determine a pattern. For example, over 10,000 threads could be executing concurrently, making pattern detection difficult.
In addition, highly multithreaded parallel processors, such as graphics processing units (GPUs), have relatively small cache capacities per thread compared to serial processors such as CPU (central processing unit) cores.
Accordingly, what is needed in the art is a cache management technique that makes effective use of the limited caching capabilities of a multithreaded parallel processor.